In many instances data must be transferred between multiple computer components or computer nodes. An example is data transfer between two microprocessors. One way to perform the data transfer is to have a set of latches in the sender microprocessor launch the data through a set of off-processor drivers and into a set of cables. The receiver microprocessor could interface to these cables through a set of off-processor receivers that first amplify the respective signals and then load them into a set of receiving latches which are strobed by a clock sent from the sender microprocessor. With this arrangement, the receiver clock and the sender clock maintain a fixed relationship in time. The off-processor drivers, the cable, and the off-processor receivers form a link between the two microprocessors. The delay times of the off-processor drivers and the off-processor receivers, and the cable length determine the latency of the link.
Although the data for each cable is launched at the same time, the data arrival times at the receiving end may be different due to variations in the link characteristics. Ideally, the data signal should be centered at the sampling edge of the received clock. Because of the variations in data arrival times, the received signals may need to be phase-aligned with respect to the sampling edge of the received clock in order to be properly captured by the receiving registers. A self-timed interface (STI) can be used to align the incoming data bits so that they will be captured by the received clock in a more reliable manner. STI is disclosed in U.S. Pat. No. 5,568,526, entitled Self Timed Interface. U.S. Pat. No. 5,568,526 is assigned to the assignee of the present invention and is incorporated herein by reference. A STI includes a clock signal that clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a clock transition is positioned in the center of the data bit cell.
An embodiment of STI can include incoming signals in the receiver microprocessor being sent to the input of a delay line with multiple taps. The delay line can consist of multiple delay elements with the output of each delay element representing a phase of the incoming signal. This allows multiple phases to be generated with progressively increasing off-sets. STI control logic selects one of these phases by locating the phase that comes closest to aligning the mid-point of the data window with the sampling edge of the received clock. A built in mechanism locks the selected phase and makes the self-adjustment dynamically. The transition edges of a data bit can be found by an edge detection mechanism such as the one disclosed in U.S. Pat. No. 5,487,095, entitled Edge Detector. U.S. Pat. No. 5,487,095 is assigned to the assignee of the present invention and is incorporated herein by reference.
In the current implementation of STI a round-off error may occur that causes the selected tap to be taken slightly too late or slightly too early relative to the mid-point of the data window.